Science & tech · 1987
How much slower did basic CMOS logic gates become when heated from room temperature to 250°C?
The tested logic cells were typically found to be up to 65% slower at 250°C than at room temperature.
Details
The study examined the switching speed of basic CMOS logic cells over a junction temperature range of 25–250°C.
Experimental measurements of capacitively loaded inverters and NAND gates made using two standard 4 μm CMOS processes were compared with theory and SPICE2G.6 simulations.
To a good approximation, a simple delineation factor ranging from 0.004 to 0.006 per °C in this study, applied to the average gate delay at a given temperature, correctly predicted that delay.
The logic cells were typically found to be up to 65% slower at 250°C than at room temperature.
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